Hi,
Not sure if this is the correct channel to ask, but I have faced an issue with metal fill script that creates the patterns overlapped violating the minimum space, and consequently generating huge number of DRC violations.
I've attached an screenshot of how it is being generated.
Please, could you help us with this issue?
TBH don't have much idea on what went wrong because I have run for other chips and it generates the fills successfully.
PD: I've also created an issue to the PDK repository where resides the scripts https://github.com/fossi-foundation/globalfoundries-pdk-libs-gf180mcu_fd_pr/issues/42
cc: @Leo Moser (mole99)@bailey@Mehdi
Hi @mole99 I am trying to use the scripts to apply fills for our chips from Chipathon 2026. It seems that it worked fine for 3 of the 4 chips. But for one of them, the metal fill somehow was create...
This may be due to project generated fill as opposed to fill generated on the top level. I've asked the team to remove it. We'll let you know what we find.
The issue was indeed the fill in one of the existing projects. Rather than creating new ones, the filler script used those filler cells, which were the wrong size. I'll see if I can fix the filler script!
1
Leo Moser (mole99)
The issue was indeed the fill in one of the existing projects. Rather than creating new ones, the filler script used those filler cells, which were the wrong size. I'll see if I can fix the filler script!
Hi @tnt thanks, I've provided the information to reproduce it in the issue itself
Leo Moser (mole99)
The issue was indeed the fill in one of the existing projects. Rather than creating new ones, the filler script used those filler cells, which were the wrong size. I'll see if I can fix the filler script!
1
1